Power management integrated circuit, power management method, mobile device and clock adjusting method

ABSTRACT

A power management approach for a mobile device includes comparing a battery provided power supply voltage to a reference voltage in order to generate an alarm signal. In response to the alarm signal the frequency of an operating clock applied to a system-on-chip is changed.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a Continuation of U.S. application Ser. No. 17/408,700, filedAug. 23, 2021, which is a Continuation of U.S. application Ser. No.16/537,869, filed Aug. 12, 2019, now U.S. Pat. No. 11,122,513 issued onSep. 14, 2021, which is a Continuation of U.S. application Ser. No.14/793,381, filed Jul. 7, 2015, now U.S. Pat. No. 10,383,062 issued onAug. 13, 2019, and a claim of priority under 35 U.S.C. § 119 is made toKorean Patent Application No. 10-2014-0111717 filed Aug. 26, 2014, thesubject matter of which is hereby incorporated by reference.

BACKGROUND

The inventive concept relates generally to power management approachesthat may be used in mobile devices. More particularly, the inventiveconcept relates to power management circuits, mobile devices includingpower management circuits, and methods of adjusting the frequency of anoperating clock in view of power supply voltage(s) provided by a batteryin the mobile device. In certain embodiments of the inventive concept,the power management circuit will be configured in a power managementintegrated circuit (PMIC) separate from a computational logic chip orSystems-on-Chip (SoC), such as those including a central processing unit(CPU) controlling the overall operation of the mobile device.

The operational reliability and effective operating duration ofbattery-powered mobile devices are increasingly importantconsiderations. That is, as users move more and more of their digitalcomputational requirements and entertainment applications to mobileplatforms, such as smart phones, smart watches, tablets, etc., the needto usefully extend battery life continues to be an important designand/or operating consideration. In this regard, the battery-poweredoperation of many mobile devices becomes particularly precarious ascharge is drained from the battery below a particular level (i.e.,circumstances that generally result in a “low battery” condition). Forexample, while many functions will continue to be normally executable ina mobile device powered by a low battery, other (more power-hungry)functions may stress the low battery to a point where the mobile devicecannot continue to operate. In this regard, a mobile device powered by alow battery becomes increasingly susceptible to operative interruptions(e.g., undesired shut-downs) caused by a sudden momentary power loss(SMPL).

A SMPL may alternately be referred to as a sudden voltage drop (SVD) andmay be the result of a certain “power events” caused when a low batteryis suddenly (or momentarily) required to provide a relatively high levelof current due to some loading effect (e.g., initiation of some highcurrent consuming functionality by a mobile device user). Whenconfronted by this sudden demand for current, a low battery may not beable to maintain at a minimum level one or more signals (e.g., controlsignals, clock signals, operating voltages, etc.), such as thosecritically provided to a processor, computational logic, centralprocessing unit, etc. This loss of minimum signal level, even during arelatively brief or transient moment, may cause the mobile device topower-down and/or operate abnormally. As a result, in the absence ofsuch transient and relatively high-current consuming power events, themobile device might operate for a considerably longer period of timedespite the low battery condition.

SUMMARY

In one aspect, embodiments of the inventive concept provide a powermanagement method for a mobile device including a battery providing apower supply voltage. The method includes; generating a negative alarmsignal when the power supply voltage is higher than a reference voltage,and generating a positive alarm signal when the power supply voltage islower than the reference voltage, and providing one of the negativealarm signal and the positive alarm signal to a System-on-Chip (SoC)including a Central Processing Unit (CPU) that operates in response toan operating clock, wherein the operating clock has a first frequency inresponse to the negative alarm signal and a second frequency lower thanthe first frequency in response to the positive alarm signal.

In another aspect, embodiments of the inventive concept provide anotherpower management method for a mobile device including a batteryproviding a power supply voltage. The method includes; generating afirst alarm signal when the power supply voltage is lower than a firstreference voltage, generating a second alarm signal when the powersupply voltage is lower than a second reference voltage, providing atleast one of the first alarm signal and the second alarm signal to aSystem-on-Chip (SoC) including a Central Processing Unit (CPU) thatoperates in response to an operating clock, wherein the operating clockhas a first frequency in response to the first alarm signal and a secondfrequency different from the first frequency in response to the secondalarm signal.

In another aspect, embodiments of the inventive concept provide a powermanagement method for a mobile device including a power managementcircuit, a System-on-Chip (SoC) including a Central Processing Unit(CPU) that operates in response to an operating clock, and a batteryproviding a power supply voltage. The method includes; communicatingpower management information from a current control unit of the SoC tothe power management circuit and storing the power managementinformation, generating a reference voltage using a reference voltagegenerator controlled by the power management circuit in response to thestored power management information, comparing the power supply voltageto the reference voltage, and if the power supply voltage is lower thanthe reference voltage, generating an alarm signal, and changing afrequency of the operating clock in response to the alarm signal.

In another aspect, embodiments of the inventive concept provide a mobiledevice including; a power management circuit that receives a powersupply voltage and compares the power supply voltage to a referencevoltage, wherein the power management circuit generates a negative alarmsignal when the power supply voltage is higher than a reference voltageand generates a positive alarm signal when the power supply voltage islower than the reference voltage, a System-on-Chip (SoC) that receivesone of the negative alarm signal and the positive alarm signal, andincludes a Central Processing Unit (CPU) that operates in response to anoperating clock, and a clock divider that generates the operating clock,wherein the operating clock is generated with a first frequency inresponse to the negative alarm signal and a second frequency lower thanthe first frequency in response to the positive alarm signal.

In another aspect, embodiments of the inventive concept provide a mobiledevice including; a battery that provides a power supply voltage, apower management integrated circuit (PMIC) that generates a first alarmsignal when the power supply voltage is lower than a first referencevoltage, and generates a second alarm signal when the power supplyvoltage is lower than a second reference voltage, and a System-on-Chip(SoC) including a Central Processing Unit (CPU) that operates inresponse to an operating clock, and a clock divider that generates theoperating clock with a first frequency in response to the first alarmsignal and generates the operating clock with a second frequencydifferent from the first frequency in response to the second alarmsignal.

In another aspect, embodiments of the inventive concept provide a mobiledevice including a battery providing a power supply voltage, a powermanagement integrated circuit (PMIC) that compares the power supplyvoltage with a reference voltage to provide a comparison signal, andgenerates an alarm signal from the comparison signal, a System-on-Chip(SoC) including a Central Processing Unit (CPU) that operates inresponse to an operating clock, a clock divider that generates theoperating clock in response to the alarm signal, and a current controlunit that generates clock division information and power managementinformation, wherein the power management information is communicatedfrom the SoC to the PMIC via an interface connection, and the PMICgenerates the comparison signal in response to the power managementinformation.

In another aspect, embodiments of the inventive concept provide aSystem-on-Chip, including a general purpose input/output pad thatreceives an alarm signal, a clock divider that selects a clock divisionratio in response to the alarm signal and divides a source clock usingthe selected clock division ratio to generate an operating clock, aninterrupt controller that generates an interrupt signal in response tothe alarm signal, and a Central Processing Unit that operates inresponse to the operating clock and the interrupt signal.

BRIEF DESCRIPTION OF THE DRAWINGS

Certain embodiments of the inventive concept are illustrated in theattached drawings in which:

FIG. 1 is a block diagram illustrating a mobile device according to anembodiment of the inventive concept;

FIG. 2 is an annotated graph that conceptually describes the operatingcontext of certain embodiments of the inventive concept in relation to asudden momentary power loss;

FIGS. 3, 4 and 5 are respective operating clock waveform diagramsillustrating various alarm signals that may be used by embodiments ofthe inventive concept;

FIG. 6 is a table listing operating clock frequencies and correspondingreference voltages that may be used in certain embodiments of theinventive concept;

FIGS. 7 and 8 are respective flow charts summarizing methods ofoperating a mobile device according to embodiments of the inventiveconcept;

FIG. 9 is a block diagram illustrating a mobile device according toanother embodiment of the inventive concept;

FIG. 10 is a block diagram further illustrating in one example the powermanagement integrated circuit (PMIC) of FIG. 9 ;

FIG. 11 is a block diagram further illustrating in one example thede-bounce logic of FIG. 10 ;

FIGS. 12 and 13 are respective flow charts summarizing methods ofoperating a mobile device according to embodiments of the inventiveconcept;

FIG. 14 is a block diagram illustrating a mobile device according tostill another embodiment of the inventive concept;

FIGS. 15 and 16 are respective flow charts summarizing methods ofoperating a mobile device according to embodiments of the inventiveconcept;

FIG. 16 is a flow chart showing a frequency adjusting method of a mobiledevice according to an embodiment of the inventive concept;

FIGS. 17, 18 and 19 are respective block diagrams illustrating mobiledevices according to still other embodiments of the inventive concept;and

FIGS. 20A, 20B and 20C are perspective views illustrating various hostdevices that may incorporate an embodiment of the inventive concept.

DETAILED DESCRIPTION

Certain embodiments of the inventive concept will now be described insome additional detail with reference to the accompanying drawings. Theinventive concept, however, may be embodied in many different forms, andshould not be construed as being limited to only the illustratedembodiments. Rather, these embodiments are provided as examples so thatthis disclosure will be thorough and complete, and will fully convey theconcept of the inventive concept to those skilled in the art.Accordingly, certain known processes, elements, and techniques are notdescribed with respect to some of the embodiments of the inventiveconcept. Throughout the written description and drawings, like referencenumbers and labels are used to denote like or similar elements, stepsand features.

It will be understood that, although the terms “first”, “second”,“third”, etc., may be used herein to describe various elements,components, regions, layers and/or sections, these elements, components,regions, layers and/or sections should not be limited by these terms.These terms are only used to distinguish one element, component, region,layer or section from another region, layer or section. Thus, a firstelement, component, region, layer or section discussed below could betermed a second element, component, region, layer or section withoutdeparting from the teachings of the inventive concept.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the inventiveconcept. As used herein, the singular forms “a”, “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises” and/or “comprising,” when used in this specification,specify the presence of stated features, integers, steps, operations,elements, and/or components, but do not preclude the presence oraddition of one or more other features, integers, steps, operations,elements, components, and/or groups thereof. As used herein, the term“and/or” includes any and all combinations of one or more of theassociated listed items. Also, the term “exemplary” is intended to referto an example or illustration.

It will be understood that when an element or layer is referred to asbeing “on”, “connected to”, “coupled to”, or “adjacent to” anotherelement or layer, it can be directly on, connected, coupled, or adjacentto the other element or layer, or intervening elements or layers may bepresent. In contrast, when an element is referred to as being “directlyon,” “directly connected to”, “directly coupled to”, or “immediatelyadjacent to” another element or layer, there are no intervening elementsor layers present.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this inventive concept belongs. Itwill be further understood that terms, such as those defined in commonlyused dictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art and/orthe present specification and will not be interpreted in an idealized oroverly formal sense unless expressly so defined herein.

FIG. 1 is a block diagram illustrating a mobile device 100 according toan embodiment of the inventive concept. Referring to FIG. 1 , the mobiledevice 100 generally comprises a power management integrated circuit(PMIC) 120 and a System-on-Chip (SoC) 130. A battery 110 configured foruse with the mobile device 100 provides one or more power supplyvoltages (hereafter, singularly or collectively referred to as “powersupply voltage”). In this regard, a “mobile device” may be understood asany device capable of being readily transported by a user, and furthercapable of operating in response to a power supply voltage provided by abattery or similar power-storing element. In contrast, devices notnormally intended for personal transportation by a user, and/or notcapable of normal operations using battery-provided power are not deemedto be mobile devices for purposes of this description.

Here, the battery 110 may be charged using one or more techniques thatuse hardwired and/or wireless connections. Thus, the battery 110 may becharged using a direct current (DC) source, an alternating current (AC)source, magnetic induction, magnetic resonance, electromagneticinduction, non-radial wireless charging, etc. In this manner, the powersupply voltage Vin may be provided to power (or drive) one or more ofthe constituent components of the mobile device 100.

As illustrated in the example of FIG. 1 , the PMIC 120 receives thepower supply voltage Vin from the battery 110, and in response maygenerate one or more operating voltage(s) applied to the SoC 130 and/orother components of the mobile device 100. (Hereafter, these one or moreoperating voltage(s) will be singularly or collectively referred to as“operating voltage”). Hence, the PMIC 120 may be said to provide anoperating voltage to the SoC 130 via one or more power supply line(s)(not shown in FIG. 1 ).

As will be described in some additional detail hereafter, the PMIC 120may include one or more register(s) or memory(s) configured to store“power management information”. Here, power management information willvary according to power management mode (e.g., normal mode, sleep mode,low-power mode, etc.), and certain power management information may beprovided to, received from, and/or derived by a component disposed inthe SoC 130. The power management information may include digitalcontrol data such as voltage settings, and/or one or more controlsignals related to condition(s) of an operating voltage and/orcondition(s) of the power supply voltage Vin, for example.

As used herein, the term “register” denotes a broad category ofcircuits, logic gates, and/or memory devices (volatile and/ornonvolatile) capable of storing one or more types of information. Suchinformation will usually take the form of digital data, but the scope ofthe inventive concept is not limited thereto. One or more physicallyseparate (and potentially disparate) circuits or component may befunctionally operated as a register, and one or more registers may bedisposed on the PMIC 120 and SoC 130 of FIG. 1 , for example.

In certain embodiments of the inventive concept, the PMIC 120 may beused to compare the power supply voltage Vin, directly or indirectlyprovided by the battery 110, with a reference voltage REF in order togenerate an alarm signal indicating, for example, a sudden voltage drop(SVD). This is just one particular example of a power management controlsignal that may be generated in response to the stored power managementinformation during operation of the mobile device 100. In theillustrated example of FIG. 1 , the SVD alarm signal is communicatedfrom the PMIC 120 to the SoC 130 via a dedicated control signal line,but this is just one possible example and the scope of the inventiveconcept is not limited thereto. Alternately, the SVD alarm signal may becommunicated from the PMIC 120 to the SoC 130 via a multiplexed signalline, a wireless link, or as part of control data arranged in a controldata packet communicated from the PMIC to the SoC.

In the illustrated example of FIG. 1 , the PMIC 120 includes a referencevoltage generator 123 and a voltage comparator 125. The referencevoltage generator 123 generates the reference voltage REF in response tostored power management information, and the voltage comparator 125compares the power supply voltage Vin with the reference voltage REF inorder to appropriately generate the SVD alarm signal.

The SoC 130 may drive one or more internal elements using the operatingvoltage received from the PMIC 120. In FIG. 1 , the SoC includes a clockdivider 132, an interrupt controller (IC) 133, and a central processingunit (CPU) 134. In certain embodiments of the inventive concept, the SoC130 may take the form of an application processor (AP). In this context,it should be noted that the CPU 134 may be implemented in many different(hardware/software/firmware) forms, such as one or more processing unitsor one or more processing cores provided by a general purpose processor.

In certain embodiments of the inventive concept, the SoC 130 willinclude a specific signal pad designated to receive the SVD alarm signalfrom the PMIC 120. Here, the term “pad” denotes one or more conductiveelement(s) configured to receive externally provided input signal(s),such as the SVD alarm signal. A pad may take many different physicalforms depending on the nature and definition of the expected inputsignal(s), but in certain embodiments of the inventive concept thedesignated signal pad will simply be a general purpose input/output(GPIO) pad.

The clock divider 132 receives an externally provided “source clock”SCLK and may be used to divide the frequency of the source clockaccording to a clock division ratio in order to generate an “operatingclock” CLK having a desired frequency. In this manner, the clock divider132 may be used to adjust, control, vary, change or convert one or morequalities (e.g., phase, frequency, duty cycle, etc.) of the operatingclock CLK in response to the state of the SVD alarm signal. For example,the clock divider 132 may be used to “divide-down” (i.e., reduce) thefrequency of the source clock SCLK to obtain an operating clock CLKhaving a desired frequency in response to the SVD alarm signal.

In one possible embodiment, the clock divider 132 may receive anddivide-down the frequency of the source clock SCLK according to a firstclock division ratio in order to obtain a first operating clock CLK1having a first frequency (f1) in response to a negative SVD alarm signal(i.e., a SVD alarm signal indicating a normal-level power supply voltageVin, that is, a power supply voltage higher than a reference voltage).Then, upon receiving a positive SVD alarm signal (i.e., a SVD alarmsignal indicating a low-level power supply voltage Vin, that is, a powersupply voltage lower than the reference voltage), the clock divider 132may be used to further divide-down the frequency of the source clockSCLK according to a second clock division ratio in order to obtain asecond operating clock CLK2 having a second frequency (f2) lower thanthe first frequency (f1). After the passing of the power event causingthe negative-to-positive SVD alarm signal transition (e.g., the powersupply voltage falling below the reference voltage), normal operatingconditions may resume, thereby causing the SVD alarm signal totransition from the positive state back to the negative state (e.g., thepower supply voltage rising above the reference voltage). Accordingly,the clock divider 132 may again be used to divide-down the frequency ofthe source clock SCLK according to a first clock division ratio in orderto again obtain the operating clock CLK1 having the first frequency(f1).

Those skilled in the art will recognize that the alarm signal may bedefined in many different ways, and therefore the positive and negativealarm signal states may be variously defined. For example, where thealarm signal is continually provided to the SoC 130 as a two logic level(i.e., high (H) and low (L)) input signal, one level (e.g., ‘H’) may bedesignated as a positive alarm signal state while the other level (e.g.,‘L’) may be designated as the negative alarm state.

The foregoing example assumes that the source clock has a frequency thatis higher than either the first or second frequencies for the operatingclock. However, this need not always be the case, and the clock divider132 may be used in certain embodiments to “divide-up” the frequency ofthe source clock SCLK using an appropriate clock division ratio in orderto obtain one or more operating clock(s) having respective frequenc(ies)higher than the frequency of the source clock SCLK.

In this regard, the clock divider 132 may include one or moreregister(s) storing clock division ratio information that defines one ormore clock division ratio(s). In the context of the foregoing example, afirst clock division ratio value may be set as a default to generate theoperating clock CLK having the first frequency (f1) that is provided tothe CPU 134 during normal battery conditions, as indicated by thenegative SVD alarm signal. In contrast, a second clock division ratiomay be set to generate the operating clock having the second frequency(f2) that is provided to the CPU 134 during low battery conditions, asindicated by the positive SVD alarm signal.

Extending this example, certain clock division ratio information may beloaded to the registers of the clock divider 132 during a power-upoperation for the mobile device 100 or during a power reset operationfor the SoC. The clock division ratio information may be externallyprovided and/or stored in a nonvolatile memory disposed in the PMIC 120or SoC 130. Alternately, the clock division ratio information may beprogrammed to one or more registers of the clock divider 132 and/orregisters or memories of the SoC 130 in response to user-providedinput(s).

In FIG. 1 , the interrupt controller 133 may be used to manageinterrupts received by the SoC 130. As will be appreciated by thoseskilled in the art, an “interrupt” is a type of input signal thatindicates a transition from one state to a different state, and/or theoccurrence of an event. For example, the interrupt controller 133 mayreceive the SVD alarm signal as one type of interrupt, and recognizeaccording to the (e.g.,) positive/negative state of the SVD alarm signalwhether the power supply voltage Vin is in a normal state or a lowstate, as suggested above. In response to the given state (or a statetransition) for the SVD alarm signal, the interrupt controller 133 maypass interrupt information (or indication) to the CPU 134.

As noted above, mobile devices conventionally suffer from undesired andunwanted power resets or power-downs caused by sudden momentary powerlosses (SMPL) that may be transient in nature and of short duration. Incontrast, embodiments of the inventive concept, like the mobile device100 described in relation to FIG. 1 , may avoid such operationalinterruptions by generating a SVD alarm signal when the power supplyvoltage Vin falls below a predetermined level, and then reducing thefrequency of one or more operating clocks CLK in response to the alarmsignal SVD.

FIG. 2 is annotated graph that conceptually describes the operatingcontext of certain embodiments of the inventive concept in relation to asudden momentary power loss.

Referring to FIGS. 1 and 2 , it is assumed that the battery 110 of themobile device 100 is a low battery having residual stored charge lessthan 20% of its normal capacity (A). With reference to the graphgenerally equating the level of the power supply voltage Vin with theoperating time for the mobile device 100, the dotted line of FIG. 2shows an expected gradual degradation in the level of Vin as the resultof continually decreasing battery charge (B). For example, this expectedpower supply voltage Vin curve may be the result of continued executionof relatively low current consuming functions by the mobile device 100.

However, a sudden voltage drop (SVD) occurs (C). Following theconventional approach, the PMIC 120 would merely initiate a power downof the mobile device 100 once the level of the power supply voltage(denoted by the dashed.dot line) falls below a minimum level due to apower event causing the SVD (D). In contrast, embodiments of theinventive concept use a power management circuit, such as the PMIC 120of FIG. 1 , to detect a low battery condition (e.g., a power supplyvoltage lower than a reference voltage), and generate an appropriatealarm signal. In response to the alarm signal, the SoC 130 in the mobiledevice 100 will automatically adjust (i.e., reduce) the frequency of anoperating clock controlling the operation of a CPU 134 (E), therebyreducing power consumption by the CPU 134.

In a power management method according to an embodiment of the inventiveconcept, when a drop of the power supply voltage Vin due to suddenvoltage/current consumption detected, the frequency of the operatingclock CLK is reduced in response to a positive SVD alarm signal, therebyeffectively extending the operating duration of the mobile device 100despite the low battery condition and the sudden momentary power loss.In this manner, the mobile device 100 of FIG. 1 and similar embodimentsof the inventive concept prevent the operation of the SoC 130 from beingsuddenly reset or powered off due to an overcurrent condition caused bya power event, whether the power event is actually detected as afunction of power supply voltage or battery condition, orcomputationally predicted. As a result, the mobile device may bettercope with a low-battery condition, thereby extending the operationallife of the mobile device between successive battery chargingoperations.

In the context of the foregoing examples, the SoC 130 of FIG. 1essentially receives the positive SVD alarm signal as a type ofhardwired interrupt signal indicating a low battery condition andprevents an unnecessary SoC power-down in response to the interrupt.This hardware approach to the immediate indication of a low batterycondition (e.g., the positive alarm signal) is superior to many softwarebased approaches conventionally used in mobile devices. Such softwarebased approaches are often too slow to prevent the abnormal operation orpower-down of the SoC 130 due to a transient power event.

FIGS. 3, 4 and 5 illustrate various forms that the alarm signal may takeaccording to embodiments of the inventive concept.

Referring first to FIGS. 1, 2 and 3 , an operating clock CLK provided tothe CPU 134 and generated by the clock divider 132 is initially assumedto have a first frequency F_CLK1. This may be a default (or normal)clock frequency used to control the operation of the CPU 134 when thePMIC 120 generates a negative SVD alarm signal indicating that the powersupply voltage Vin is higher than a defined reference voltage REF.However, when the power supply voltage Vin falls below the referencevoltage, the PMIC 120 transitions the negative SVD alarm signal to apositive SVD alarm signal, and in response to the positive SVD alarmsignal, the clock divider 132 adjusts the frequency of the operatingclock CLK to be a second frequency F_CLK2, less than the first frequencyF_CLK1.

As shown in FIG. 3 , two (2) distinct sudden momentary power losses(SMPLs) occur during operation of the mobile device 100—a first SMPLoccurring during a first period TD1 and a second SMPL occurring during ssecond period TD2. In both instances, the clock divider 132 adjusts thefrequency of the operating clock CLK from the first frequency F_CLK1 tothe second frequency F_CLK2 in response to respective activations of thepositive SVD alarm signal. Following the end of each SMPL (i.e., oncethe level of the power supply voltage returns above the referencevoltage), the clock divider 132 re-adjusts the frequency of theoperating clock CLK from the second frequency F_CLK2 to the firstfrequency F_CLK1 in response to respective deactivations of the positiveSVD alarm signal (or transitions back to the negative alarm signal).

Note in FIG. 3 that the respective durations of the first period TD1 andsecond period TD2 are different, as might be expected for different SMPLevents. However, in certain embodiments of the inventive concept, theclock divider 132 may be set a positive alarm signal duration to have afixed, predetermined duration, where each period of positive alarmsignal is begun upon detection of a SMPL (e.g., transition or activationof a positive alarm signal).

The approach illustrated in FIG. 3 assumes the use of only two (2)possible frequencies (F_CLK1, and F_CLK2) for the operating clock CLK.One of these two frequencies is effectively selected by the state(negative/positive) of an alarm signal derived from a comparison of thepower supply voltage with a single (fixed or variable) reference voltageREF. However, the scope of the inventive concept is not limited to thissimple example. Indeed, embodiments of the inventive concept may usemultiple reference voltages compared with multiple power supply voltagesthat activate one or more alarm signals selecting a particular operatingclock frequency from a plurality of operating clock frequencies. Thatis, the power management information stored in the PMIC 120 and/or SoC130 may be used to define different reference voltages, and the clockdivision information stored in the PMIC 120 and/or SoC 130 may be usedto define different operating voltage frequencies, phases, duty cycles,activation periods, etc.

FIG. 4 is a conceptual diagram describing another approach to themanagement of power consumption in a mobile device that variably adjuststhe frequency of an operating clock controlling a CPU according toembodiments of the inventive concept.

Here, it is assumed that the PMIC 120 is modified to generate a firstalarm signal SVD1 and a second alarm signal SVD2 having distinct natures(e.g., different digital codes or different voltage levels) in responseto the comparison of one or more power supply voltages to two respectivereference voltages (REF1 and REF2).

Accordingly, the first alarm signal SVD1 is generated when the powersupply voltage Vin falls below a first reference voltage (REF1), and inresponse to the first alarm signal SVD1, the clock divider 132 adjuststhe frequency of the operating clock CLK from a first frequency F_CLK1to a second frequency F_CLK2 during a third period TD3. Similarly, thesecond alarm signal SVD2 is generated when the power supply voltage Vinfalls below a second reference voltage (REF2) (e.g., less than the firstreference voltage (REF1)), and in response to the second alarm signalSVD2, the clock divider 132 adjusts the frequency of the operating clockCLK from the first frequency F_CLK1 to a third frequency F_CLK3 during afourth period TD4.

In the example illustrated in FIG. 4 , only two alarm signals are shown.However, those skilled in the art will recognize that three of moredistinct alarm signals might be used in relation to three or morereference voltage s to generate an operating clock having acorresponding frequency, phase, duty cycle, activation period, etc.

FIG. 5 is a conceptual diagram describing another approach to themanagement of power consumption in a mobile device that variably adjuststhe frequency of an operating clock controlling a CPU according toembodiments of the inventive concept.

However, in the illustrated example of FIG. 5 , the single frequencyoperating clocks of FIGS. 3 and 4 are replaced by operating clockshaving a compound set of frequencies (i.e., a set of two or moredifferent frequencies). The compound set of frequencies specificallyillustrated in FIG. 5 may be characterized as a stepped,increasing-level set of frequencies, however other compound signal formsmay be used.

Thus, upon receiving an appropriately defined SVD alarm signal, theclock divider 132 will initially adjust the operating clock CLK to havea fourth operating frequency F_CLK4, and thereafter following apredetermined delay, the clock divider 132 will further adjust theoperating clock to have a fifth operating frequency F_CLK5, differentfrom (e.g., higher then) the fourth operating frequency F_CLK4.

From the foregoing, it will be understood that many different types ofoperating clocks (and corresponding reference voltages) may be used invarious embodiments of the inventive concept. FIG. 6 is a table listingdifferent operating clock frequencies (CPU CLK) and correspondingreference voltages (REF). Referring to FIG. 6 , the listed operatingfrequency range from 2.00 GHz when a reference voltage of 1.2 V is used,to 1.50 GHz when a reference voltage of 1.1 V is used, and to 1.33 GHzwhen a reference voltage of 1.0 V is used.

Thus, referring to FIGS. 1 and 6 , the CPU 134 will be driven by a 2.00GHz operating clock so long as the power supply voltage Vin stays above1.2 V, by a 1.50 GHz operating clock when the power supply voltage Vinranges below 1.2V but stays above 1.1 V, and by a 1.33 GHz operatingclock when the power supply voltage Vin ranges below 1.1V but staysabove 1.0 V. And in certain embodiments of the inventive conceptconsistent with the listed examples of FIG. 6 , the mobile device 100may be powered down when the power supply voltage falls below 1.0 V. Inthis manner, current consumption by the CPU 134 of the SoC 130 in mobiledevice 100 may be conserved by use of a sequentially stepped-downoperating clock frequency as the level of the power supply voltage Vinfalls below successively reduced reference voltages.

FIG. 7 is a flowchart summarizing a method of operating a mobile deviceaccording to an embodiment of the inventive concept. Referring to FIGS.1 and 7 , a power management circuit, such as PMIC 120, determineswhether a power supply voltage Vin provided by the battery 110 is lowerthan a reference voltage REF (S110). When the power supply voltage Vinis lower than the reference voltage REF (S110=Yes), the power managementcircuit generates a SVD alarm signal (S120). Then, the clock divider 132of the SoC 130 divides a source clock SCLK using a predetermined clockdivision ratio in response to the SVD alarm signal (S130). In thismanner, the clock divider 132 adjusts the frequency of the operatingclock CLK in response to the SVD alarm signal.

FIG. 8 is another flowchart further summarizing the method of operatingthe mobile device 100 according to an embodiment of the inventiveconcept. Referring to FIGS. 1 and 8 , the clock divider 132 receives theSVD alarm signal from the power management circuit (S210), and dividesthe source clock SCLK using the predetermined clock division ratio inresponse to the SVD alarm signal (S220). Once adjusted in this manner,the operating CLK is provided to the central processing unit (CPU) 134of the SoC (S230). In this manner, the operating clock having anappropriately adjusted frequency is applied to a computational logiccircuit of the SoC 130 to reduce power consumption within the mobiledevice 100.

A previously suggested the fixed-level reference voltage (REF) assumedin the foregoing embodiments may be varied according to power managementinformation in certain embodiments of the inventive concept.

FIG. 9 is a block diagram illustrating a mobile device 200 according toanother embodiment of the inventive concept. Referring to FIG. 9 ,mobile device 200 includes a battery 210, a power management integratedcircuit (PMIC) 220, and a System-on-Chip (SoC) 230.

The PMIC 220 includes a reference voltage generator 223 and a comparator225. However, the PMIC 220 and the SoC 230 of FIG. 9 are further enabledto communicate power management information via an interface connection205. Thus, the PMIC 220 includes a PMIC interface 221 configured toreceive power management information from a SoC interface 231. Here, theinterface connection 205 may be a hardwired and/or a wireless connectionbetween the PMIC 220 and SoC 230, and may be used in certain embodimentsof the inventive concept to serially communicate the power managementinformation (e.g., via a Serial Peripheral Interface (SPI) or an InterIntegrated Circuit—I2C) between the SoC 230 and PMIC 220.

Using the interface connection 205, power management information (e.g.,information defining reference voltage levels) may be communicated fromthe SoC 230 to the PMIC 220 in real-time, in near real-time, orperiodically to dynamically adjust the level of the referencevoltages(s) used by the PMIC 220 to generate the SVD alarm signal.Accordingly, in addition to the clock divider 232, interrupt controller233 and CPU 234, the SoC 230 of FIG. 9 includes a SoC interface 231 anda current control unit 235.

With this configuration when a power event is detected or predicted, thecurrent control unit 235 may generate (or update) power managementinformation to be communicated to the PMIC 220 in order to appropriatelyset the level of one or more reference voltages. The current controlunit 235 may also generate clock division ratio information used todefine one or more clock division ratios used by the clock divider 232to generate one or more operating clocks having respective desiredfrequencies. The current control unit 235 may be implemented using anyreasonable combination of software, hardware and/or firmware.

In this manner, the mobile device 200 may use the PMIC 220 todynamically adjust (or change) the level of one or more referencevoltage(s) in response to real-time, near real-time, or periodicallyupdated power management information generated by the current controlunit 235 of the SoC 230. In certain embodiments of the inventiveconcept, the interface connection 205 may be a two-way interfaceconnection enabling the PMIC 220 to communicate status informationand/or feedback information to the SoC 230 related to a power supplysignal, constituent battery, etc.

FIG. 10 is a block diagram further illustrating in one example the PMIC220 of FIG. 9 . Referring to FIG. 10 , the PMIC 220 includes an I2Cinterface circuit 221, a register 222, a reference voltage generator223, a multiplexer 224, a voltage comparator 225, de-bounce logic 226,and an open drain pad 227.

The PMIC interface (e.g., I2C interface circuit) 221 receives powermanagement information (e.g., information defining one or more referencevoltage levels) via a serial data communication protocol from anexternal device (e.g., SoC 230 in FIG. 9 ). Thus, in the illustratedembodiment of FIG. 10 , the PMIC interface 221 receives both anexternally provided serial clock at a serial data port (SCL) andexternally provided serial data at a serial data port (SDA).

The register 222 may include a plurality of individual data registers orsimilar circuitry configured to store the power management informationin the form of control data. In this regard, the register 222 receivesthe power management information from the PMIC interface 221. Here, inone simple example related to the embodiment of FIG. 10 , the powermanagement information is assumed to include a first part (e.g., 3 bits)provided to the multiplexer 224, a second part (2 bits) provided to thecomparator 225, and a third part (e.g., 6 bits) provided to debouncelogic 226.

In the illustrated example of FIG. 10 it is further assumed that thereference voltage generator 223 is configured to generate a plurality(e.g., eight) of reference voltages, that are respectively selected bythe multiplexer 224 in response to the first part (3 bit) of the powermanagement information provided by the register 222. The comparator 225compares the power supply voltage Vin provided to the battery power pad(VBAT) with the reference voltage REF selected by the multiplexer 224.Here, the hysteresis level of the voltage comparator 225 is selected bythe second part (e.g., 2 bits) of the power management informationprovided by the register 222.

The debounce logic 226 is a type of circuit commonly used to reduce orremove a bounced signal portion (i.e., signal chatter) from thecomparison signal (CMP_OUT) provided by the comparator 225. Theresponsiveness of the debounce logic 226 is controlled by de-bouncetiming information (i.e., the third part of the power managementinformation). For example, the debounce logic 226 may be used togenerate a valid alarm signal SVD when the comparison signal ismaintained during a predetermined debounce time, where the debounce timeis a defined period of time after which a sustained level (e.g., ‘H’ or‘L’) of the comparison signal is recognized as a valid (e.g., normal/lowbattery or positive/negative) SVD alarm signal. In this manner, thedebounce logic 226 reduces signal bounce in proportion to respectivedebounce times selected by the third part of the power managementinformation.

The open drain pad 227 outputs the SVD alarm signal to a signal pad(LOWBAT), for example, in response to the debounced comparison signalprovided by the debounce logic 226. The open drain pad 227 illustratedin FIG. 10 includes a transistor MT, first and second diodes D1 and D2,and the signal pad. The transistor is connected between the signal padand a ground terminal GND and is turned ON/OFF in response to thedebounced comparison signal provided by the debounce logic 226. Thefirst diode D1 is connected between the signal pad and the groundterminal and the second diode D2 is connected between a power supplyterminal VDD and the signal pad.

FIG. 11 is a block diagram further illustrating in one example thedebounce logic 226 of FIG. 10 . Referring to FIG. 11 , debounce logic226 includes a counter 226-1, an AND logic gate 226-2, and a flip-flop226-3.

The counter 226-1 receives a sampling clock (SMP_CLK), as well as thecomparison signal from the comparator 225 and target counter bit data(e.g., the third part of the power management information). In responseto these input signals, the counter 226-1 counts the comparison signalusing a counter responsive to the target counter bit data. In thismanner, different debounce times may be applied to the counter(s).

The AND gate 226-2 performs an AND operation on a match value (i.e., theoutput value of the counter 226-1) and the sampling clock. The resultingoutput of the AND gate 226-2 is used to enable (or synchronize) theflip-flop 226-3 that provides the debounced comparison signal.

With the above-described configuration, the debounce logic 226 reducesor removes a bounced signal portion of the comparison signal in responseto the target counter bit data in order to provide a reliable alarmsignal.

FIG. 12 is a flowchart summarizing a method of operating a mobile deviceaccording to another embodiment of the inventive concept. With referenceto FIGS. 9 and 12 , the current control unit 235 generates powermanagement information in response to the detection/non-detection orprediction/non-prediction of a power event, such as a low batterycondition, user-initiation of a high current consuming function, etc. Inresponse to the power management information provided by the currentcontrol unit 235, the PMIC 220 sets the level of a reference voltage REF(S305). Then, the power supply voltage Vin is compared with thereference voltage (S310). Upon determining that the power supply voltageVin is lower than the reference voltage REF (S310=Yes), a correspondingdebounced comparison signal is generated and provided as a SVD alarmsignal (S320). Then, in response to the SVD alarm signal, the clockdivider 232 adjusts the frequency of the operating clock CLK provided tothe CPU 234 (S330). This may be accomplished by dividing anexternally-provided source clock SCLK with a clock division ratioselected in response to the SVD alarm signal. Alternately, the operatingclock frequency may be maintained at a given (e.g., default) frequencywhen the power supply voltage Vin is higher than the reference voltageREF.

According to the foregoing embodiments, one or more reference voltage(s)used by a power management circuit, such as PMIC 220 of FIG. 9 , may bevariously defined by power management information received via aninterface connection 205 between the PMIC 220 and the SoC 230. In suchembodiments, a current control unit 235 may be used to provide not onlypower management information to the PMIC 220, but also clock divisionratio information to the clock divider 232.

FIG. 13 is another flowchart summarizing a method of operating a mobiledevice according to still another embodiment of the inventive concept.The steps of the method shown in FIG. 13 are respectively analogous tothe steps of the method shown in FIG. 12 , except that clock divisionratio information, as well as reference voltage information is generatedand respectively communicated to the clock divider 232 and the PMICregister 222 in step S405.

Thus, in certain embodiments of the inventive concept like thosedescribed in relation to the foregoing drawings, power may beeffectively managed in a mobile device by adjusting the frequency of anoperating clock provided to a CPU in response to an SVD alarm signal.

FIG. 14 is a block diagram illustrating a mobile device according tostill another embodiment of the inventive concept. Referring to FIG. 14, a mobile device 300 analogously includes, per the foregoingembodiment, a battery 310, a power management integrated circuit (PMIC)320, and a System-on-Chip 330. However, in addition to the clock divider332, current control unit 335, interrupt controller 333, the SoC 330 ofFIG. 14 includes a Graphics Processing Unit (GPU) 336 that is physicallyseparate from the CPU 334. The PMIC 320 and SoC 330 are connected via aninterface connection 331/321.

Here, the operating clock CLK) provided to the CPU 334 may be the sameas (or different from) the operating clock provided to the GPU 336. Thatis, in certain embodiments of the inventive concept, the clock divider332 may divide a source clock using one clock division ratio to generatea first operating clock provided to the CPU 334, and also divide thesource clock using a second clock division ratio to generate a secondoperating clock provided to the GPU 336. The definition of first/secondclock division ratios and first/second operating clocks may be a matterof operational priority assigned to the CPU 334 and GPU 336. Therefore,in response to a received alarm signal(s) the respective operatingclocks may be adjusted differently and/or according to differentadjustment timing.

FIG. 15 is a flowchart summarizing yet another method of operating amobile device according to a further embodiment of the inventiveconcept. Referring to the foregoing embodiments and FIGS. 14 and 15 ,the current control unit 335 predicts a power event (e.g., a peakcurrent or amount of current associated with some event) (S510). Thecurrent control unit 335 may also generate power management informationestablishing a reference voltage, as well as clock division ratioinformation (S520). Thereafter, the clock division ratio, as stored inthe clock divider 332, may be used to generate an operating clock ofdesired frequency in response to an alarm signal (S530).

FIG. 16 is a flowchart summarizing still another method of operating amobile device according to an embodiment of the inventive concept.Referring to the foregoing embodiments and FIG. 16 , a power event isdetected in relation to the battery condition, or mobile deviceoperating condition (S610). The nature and mode of detection for powerevents will vary by applications, but many power events will beassociated with high current demand, or weaken battery conditions. Inview of a detected power event, a SVD alarm signal SVD is received(S620), and in response, the frequency of an operating clock provided toa CPU is decreased (S630). Once the power event has passed, theoperating clock frequency may be increased (S640). Using this approach,one or more reference voltages used to generate one or more alarmsignals may be optimized to a detected power event and associatedconditions.

In the foregoing embodiments, an operating clock is generated byappropriately dividing a source clock frequency using a selected clockdivision ratio. However, the one or more operating clocks contemplatedby the inventive concept may be otherwise generated and/or frequencycontrolled. For example, certain SoC used in certain embodiments of theinventive concept may internally generate an operating clock.

FIG. 17 is a block diagram illustrating a mobile device according tostill another embodiment of the inventive concept. Referring to FIG. 17, a mobile device 400 includes a battery 410, a power managementintegrated circuit (PMIC) 420, and a System-on-Chip (SoC) 430. The PMIC420 is analogously configured with a comparator 425 and referencevoltage generator 423. However, the SoC 430 includes a clock generator432 that internally generates an operating clock in response to a SVDalarm signal as described above and under the control of a clock controlunit 434. Otherwise the elements shown in FIG. 17 are analogous to thoseshown in FIG. 14 .

As has been previously noted, the SoC described above may be configuredand operated within a mobile device as an application processor. FIG. 18is a block diagram illustrating a mobile device according to a furtherembodiment of the inventive concept. Referring to FIG. 18 , a mobiledevice 500 includes an application processor (AP) 510, a memory device520, a storage device 530, and a power management integrated circuit 580for providing an operating voltage to function modules 540 through 570respectively.

The application processor 510 controls an overall operation of themobile device 500. That is, the application processor 510 controls thememory device 520, the storage device 530, and the function modules 540through 570.

The application processor 510 may be used to detect and/or predictvarious operating states associated with the constituent centralprocessing unit(s). Thus, the application processor 510 may be used toperforms one or more operations including; providing power managementinformation, providing clock division ratio information, predicting ordetecting a power event associated with the central processing unit(s),and adjusting one or more operating clocks provided to circuitry of theapplication processor 510 depending on a predicted or detected powerevent. Those skilled in the art will recognize that the applicationprocessor 520 may be variously implemented using hardware, softwareand/or firmware.

The application processor 510 may include a clock management unit thatprovides the power management information to the power managementintegrated circuit 580 and changes an operating frequency of theapplication processor 510 with the clock division ratio information.

The power management integrated circuit 580 receives the referencevoltage setting information, detects a power supply voltage Vin of abattery, and generates an alarm signal SVD depending on the detectionresult. Thus, interaction between the application processor 510 and thepower management integrated circuit 580 may be performed at high speed.This means that dynamic frequency scaling is performed in real timedepending on the alarm signal SVD.

The memory device 520 and the storage device 530 store pieces of dataneeded for an operation of the mobile device 500. For example, thememory device 520 may be a random access memory device, such as DRAM,SRAM, mobile DRAM, or PRAM. The storage device 530 may be a nonvolatilememory device, such as EPROM, EEPROM, PRAM, flash memory, RRAM, NFGM(nano floating gate memory), PoRAM (polymer random access memory), MRAM,or FRAM.

In other exemplary embodiments, the storage device 530 may furtherinclude a solid state drive (SSD), a hard disk drive (HDD), CD-ROM, andso on.

The function modules 540 through 570 perform various functions of themobile device 500. For example, the mobile device 500 may include acommunication module 540 for a communication function, a camera module550 for a camera function, a display module 560 for a display function,and a touch panel module 570 for a touch input function. Thecommunication module 540, for example, may be CDMA (code divisionmultiple access), LTE (long term evolution), RF (radio frequency), UWB(ultra wideband), WLAN (wireless local area network), or WIMAX(worldwide interoperability for microwave access) module.

In other exemplary embodiments, the mobile device 500 may furtherinclude a GPS (global positioning system) module, a microphone module, aspeaker module, a gyroscope module, and so on. Types of the functionmodules 540 through 570 that the mobile device 500 includes may not belimited thereto.

The mobile device 500 includes the application processor 510 that iscapable of detecting or predicting power events that may necessitate theadjustment of an operating state of a central processing unit in theapplication processor 510 by changing the frequency of an operatingclock provided to circuitry of the application processor 510, therebyimproving overall system performance.

Other embodiments of the inventive concept provide a mobile deviceincluding a processor, such as an application processor chip, integratedwith a communication chip.

FIG. 19 is a block diagram illustrating a mobile device according to afurther embodiment of the inventive concept. Referring to FIG. 19 , amobile device 600 includes a battery 602, a power management integratedcircuit 604, an integrated processor (ModAP) 610, a buffer memory 620, adisplay/touch module 630, and a storage device 640.

The battery 602 provides a power supply voltage Vin, and the powermanagement integrated circuit 604 generates operating voltages using thepower supply voltage Vin. In particular, the power management integratedcircuit 604 generates an alarm signal SVD when the power supply voltageVin is lower than a reference voltage REF. The integrated processor 610controls an overall operation of the mobile device 600 and wire/wirelesscommunications with an external device. In particular, the integratedprocessor 610 downs a frequency of an operating clock in response to thealarm signal SVD. The buffer memory 620 temporarily stores data neededfor an operation of the mobile device 600. The display/touch module 630displays data that the integrated processor 610 processes or receivesdata from a touch panel. The storage device 640 stores user data. Thestorage device 640 may be eMMC, SSD, or UFS.

The above-described mobile devices 100, 200, 300, 400 , 500 and 600 maybe applied to a variety of electronic devices, such as a smart phone, awearable watch, and a smart glass, as illustrated in FIGS. 20A, 20B, and20C.

Power management (or clock adjustment) approaches according toembodiments of the inventive concept are not limited to only thosecomparing a power supply voltage Vin provided by a battery. Rather,embodiments of the inventive concept may be applied to other types ofpower signals originating from other sources.

While the inventive concept has been described with reference toexemplary embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the scope of the following claims.

What is claimed is:
 1. A system-on-chip (SOC) comprising: a clockdivider configured to receive a source clock and to generate anoperating clock by dividing the source clock, the source clock beingexternally provided; a central processing unit (CPU) configured toreceive the operating clock and to operate in response to the operatingclock; and an interrupt controller configured to receive one of a firstalarm signal and a second alarm signal and to send an interrupt signalto the CPU in response to receiving the second alarm signal, the firstalarm signal and the second alarm signal being externally provided,wherein the clock divider is further configured to receive one of thefirst alarm signal and the second alarm signal, to generate theoperating clock having a first frequency in response to receiving thefirst alarm signal, and to generate the operating clock having a secondfrequency in response to receiving the second alarm signal, the secondfrequency being less than the first frequency.
 2. The SOC of claim 1,wherein the CPU is further configured to consume a first magnitude ofpower in response to receiving the interrupt signal, the first magnitudeof power being less than a second magnitude of power consumed by the CPUwithout the interrupt signal.
 3. The SOC of claim 1, wherein the clockdivider is further configured to receive one of the first alarm signal,the second alarm signal and a third alarm signal and to generate theoperating clock having a third frequency in response to receiving thethird alarm signal, the third frequency being less than the secondfrequency.
 4. The SOC of claim 1, wherein the clock divider is furtherconfigured to generate the operating clock having a third frequencyafter a delay from generating the operating clock having the secondfrequency in response to receiving the second alarm signal, the thirdfrequency being higher than the second frequency.
 5. The SOC of claim 1,wherein the clock divider is further configured to generate theoperating clock having a third frequency in response to that a powersupply voltage decrease, the third frequency being less than the secondfrequency.
 6. The SOC of claim 1, wherein the clock divider is furtherconfigured to receive the first alarm signal, the second alarm signaland a power supply from an external power management integrated circuit.7. A system-on-chip (SOC) comprising: a clock divider configured toreceive a source clock and to generate an operating clock by dividingthe source clock, the source clock being externally provided; a centralprocessing unit (CPU) configured to receive the operating clock and tooperate in response to the operating clock; an interrupt controllerconfigured to receive one of a first alarm signal and a second alarmsignal and to send an interrupt signal to the CPU in response toreceiving the second alarm signal, the first alarm signal and the secondalarm signal being externally provided; and a control unit configured togenerate a power management information indicating a level of a voltagein response to the second alarm signal, the power management informationbeing communicated with an external device, wherein the clock divider isfurther configured to receive one of the first alarm signal and thesecond alarm signal, to generate the operating clock having a firstfrequency in response to receiving the first alarm signal, and togenerate the operating clock having a second frequency in response toreceiving the second alarm signal, the second frequency being less thanthe first frequency.
 8. The SOC of claim 7, wherein the control unit isfurther configured to generate a clock division ratio information inresponse to the second alarm signal, the clock division ratioinformation being provided to the clock divider.
 9. The SOC of claim 8,wherein the clock divider is further configured to receive one of thefirst alarm signal, the second alarm signal and a third alarm signal andto generate the operating clock having a third frequency in response toreceiving the third alarm signal, the third frequency being less thanthe second frequency, and wherein the clock division ratio include afirst clock division ratio corresponding to the second frequency and asecond clock division ratio corresponding to the third frequency. 10.The SOC of claim 8, wherein the clock divider is further configured togenerate the operating clock having a third frequency after a delay fromgenerating the operating clock having the second frequency in responseto receiving the second alarm signal, the third frequency being higherthan the second frequency, and wherein the clock division ratio includea first clock division ratio corresponding to the second frequency and asecond clock division ratio corresponding to the third frequency. 11.The SOC of claim 8, wherein the clock divider is further configured togenerate the operating clock having a third frequency in response tothat a power supply voltage decrease, the third frequency being lessthan the second frequency, and wherein the clock division ratio includea first clock division ratio corresponding to the second frequency and asecond clock division ratio corresponding to the third frequency. 12.The SOC of claim 7, wherein the clock divider is further configured toreceive the first alarm signal, the second alarm signal and a powersupply from an external power management integrated circuit, and whereinthe power management information is communicated with the external powermanagement integrated circuit.
 13. A system-on-chip (SOC) comprising: aclock divider configured to receive a source clock, to generate a firstoperating clock by dividing the source clock, and to generate a secondoperating clock by dividing the source clock, the source clock beingexternally provided; a central processing unit (CPU) configured toreceive the first operating clock and to operate in response to thefirst operating clock; a graphics processing unit (GPU) configured toreceive the second operating clock and to operate in response to thesecond operating clock; an interrupt controller configured to receiveone of a first alarm signal and a second alarm signal and to send aninterrupt signal to the CPU in response to receiving the second alarmsignal, the first alarm signal and the second alarm signal beingexternally provided, wherein the clock divider is further configured toreceive one of the first alarm signal and the second alarm signal, togenerate the first operating clock having a first frequency in responseto receiving the first alarm signal, to generate the first operatingclock having a second frequency in response to receiving the secondalarm signal, to generate the second operating clock having a thirdfrequency in response to receiving the first alarm signal, and togenerate the second operating clock having a fourth frequency inresponse to receiving the second alarm signal, the second frequency andthe fourth frequency being less than the first frequency and the thirdfrequency respectively.
 14. The SOC of claim 13, wherein the clockdivider is further configured to receive one of the first alarm signal,the second alarm signal and a third alarm signal, to generate the firstoperating clock having a fifth frequency in response to receiving thethird alarm signal, and to generate the second operating clock having asixth frequency, the fifth frequency and the sixth frequency being lessthan the second frequency and the fourth frequency respectively.
 15. TheSOC of claim 13, wherein the clock divider is further configured togenerate the first operating clock having a fifth frequency after afirst delay from generating the first operating clock having the secondfrequency in response to receiving the second alarm signal, and togenerate the second operating clock having a sixth frequency after asecond delay from generating the second operating clock having thefourth frequency in response to receiving the second alarm signal, thefifth frequency and the sixth frequency being higher than the secondfrequency and the fourth frequency respectively.
 16. The SOC of claim13, wherein the clock divider is further configured to generate thefirst operating clock having a fifth frequency and to generate thesecond operating clock having a sixth frequency in response to that apower supply voltage decrease, the fifth frequency and the sixthfrequency being less than the second frequency and the fourth frequencyrespectively.
 17. The SOC of claim 13, further comprising: a controlunit configured to generate a power management information indicating alevel of a voltage in response to the second alarm signal, the powermanagement information being communicated with an external device. 18.The SOC of claim 17, wherein the control unit is further configured togenerate a clock division ratio information in response to the secondalarm signal, the clock division ratio information being provided to theclock divider.
 19. The SOC of claim 18, wherein the clock divider isfurther configured to receive one of the first alarm signal, the secondalarm signal and a third alarm signal, to generate the first operatingclock having a fifth frequency in response to receiving the third alarmsignal, and to generate the second operating clock having a sixthfrequency, the fifth frequency and the sixth frequency being less thanthe second frequency and the fourth frequency respectively, and whereinthe clock division ratio include a first clock division ratiocorresponding to the second frequency. a second clock division ratiocorresponding to the fourth frequency, a third clock division ratiocorresponding to the fifth frequency, and a fourth clock division ratiocorresponding to the sixth frequency.
 20. The SOC of claim 18, whereinthe clock divider is further configured to generate the first operatingclock having a fifth frequency after a first delay from generating thefirst operating clock having the second frequency in response toreceiving the second alarm signal, and to generate the second operatingclock having a sixth frequency after a second delay from generating thesecond operating clock having the fourth frequency in response toreceiving the second alarm signal, the fifth frequency and the sixthfrequency being higher than the second frequency and the fourthfrequency respectively, wherein the clock division ratio include a firstclock division ratio corresponding to the second frequency. a secondclock division ratio corresponding to the fourth frequency, a thirdclock division ratio corresponding to the fifth frequency, and a fourthclock division ratio corresponding to the sixth frequency.